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1 standard ics driver for segmented lcd module with key input function BU9768AK / BU9768AKv the BU9768AK / BU9768AKv are man-machine interface ics with key input, designed for portable multimedia termi- nals and other devices. they can be used as drivers for operation mode display lcd panels on portable terminals, household products, car stereos, and other appliances. up to 126 cells can be displayed, and up to 30 keys can be input. also, a maximum of four outputs are possible using expansion pins. (the number of outputs for each pin can be changed using control codes.) applications portable multi-media terminals, pos terminals, wireless radios, telephones, cameras, vcrs, movie projectors, car stereos, others features block diagram key scan control key scan buffer command decoder lcd power o.s.c divider control decoder control register shift register data latch for lcd segment and common driver kl 1 do cs dl ck v dd v ss osc rst com 1 com 3 s 1 (ep 1 )s 4 (ep 4 )s 5 s 40 v dd1 v dd2 kl 2 ko 1 (s 41 ) ko 2 (s 42 ) ko 3 ko 4 ko 5 ko 6 kl 3 kl 4 kl 5 1) drive of up to 42 segment outputs, three common outputs, and up to 126 cells is possible. 2) up to 30 keys can be input. 3) a maximum of four pins can be used as output pins for expansion. 4) 1 / 3 duty drive. 5) a bias of 1 / 2 or 1 / 3 can be selected for the lcd display power supply.
2 standard ics BU9768AK / BU9768AKv pin assignments 48 12345678910111213141516 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ko 5 ko 4 ko 3 ko 2 (s 42 ) ko 1 (s 41 ) com 3 com 2 com 1 s 40 s 39 s 38 s 37 s 36 s 35 s 34 s 33 s 1 (ep 1 ) s 2 (ep 2 ) s 3 (ep 3 ) s 4 (ep 4 ) s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 ko 6 kl 1 kl 2 kl 3 kl 4 kl 5 rst v dd v dd1 v dd2 v ss osc do cs ck di 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 s 32 s 31 s 30 s 29 s 28 s 27 s 26 s 25 s 24 s 23 s 22 s 21 s 20 s 19 s 18 s 17 fig.1
3 standard ics BU9768AK / BU9768AKv pin descriptions pin no. pin name function i / o processing if not used 1 ~ 4 s 1 (ep 1 ) ~ s 4 (ep 4 ) o common output pins key scan output pins key scan input pins oscillator pin for segment / common alternating waveforms chip select input pin synchronous clock input pin for data transmission data input pin for lcd display open 5 ~ 40 s 5 ~ s 40 o open 41 ~ 43 com 1 ~ com 3 o open 44, 45 ko 1 (s 41 ), ko 2 (s 42 ) o open 46 ~ 49 ko 3 ~ ko 6 o open 50 ~ 54 ki 1 ~ ki 5 i open 55 rst i v dd 57 v dd 1 58 v dd 2 60 osc 61 do o open 62 cs i v ss 63 ck i v ss 64 di i v ss reset input pin for low active state. segment and common outputs are fixed at low level while rst is low, and all displays disappear. data for lcd displays is not reset. all data in the key scan buffer is cleared. key buffer data output pin. after a key scan has been completed, if key input existed, this changes to low. also, if the key data communications command is input, the contents of the key buffer are output as serial data. since this is open drain output, it should be used with a pull-up resistor. output pins for switching between segment output and expansion pin output. switched using control codes p 0 and p 1 . when expansion pins are used, these output set data (1 or 0). segment output pins. these output waveforms correspond to serial data input from di. internal reference voltage for lcd. when using in the 1 / 2 bias mode, this should be connected to v dd1 . internal reference voltage for lcd. when using in the 1 / 2 bias mode, this should be connected to v dd2 . output pins for switching between key scan output and segment output. switching is enabled using control codes k 0 and k 1 . absolute maximum ratings (ta = 25?) parameter symbol power supply voltage input voltage output voltage output current storage temperature v dd v in v out i out (1) i out (2) i out (3) i out (4) p d t stg v dd rst, osc, cs, ck, di, ki 1 ~ ki 5 osc, do, ko 1 ~ ko 6 , ep 1 ~ ep 4 com 1 ~ com 3 ep 1 ~ ep 4 s 1 ~ s 40 ko 1 ~ ko 6 limits pin unit ?0.3 ~ + 7.0 ?0.3 ~ v dd + 0.3 ?0.3 ~ v dd + 0.3 ?55 ~ + 125 * this is the maximum voltage which may be applied to the v ss pin. reduced by 8.0mw (ak) or 7.5mw (akv) for each increase in ta of 1 c over 25 c. BU9768AK BU9768AKv 3 5 300 1 800 750 power dissipation v v v ma ma m a ma mw * c
4 standard ics BU9768AK / BU9768AKv recommended operating conditions (ta = 25?) parameter symbol unit max. typ. min. pin v dd topr v dd + 4.5 ?40 + 6.0 + 85 v c power supply voltage operating temperature electrical characteristics (unless otherwise noted, v dd = 4.5v to 6.0v, ta = 25?) parameter symbol min. typ. max. unit conditions input high level voltage input low level voltage input high level current input low level current input floating voltage pull-down resistance output off leakage current output high level voltage output low level voltage output intermediate level voltage power supply current v ih (1) v ih (2) v il (1) v il (2) i ih i il v if r pd i offh v oh (1) v oh (2) v oh (3) v oh (4) v ol (1) v ol (2) v ol (3) v ol (4) v ol (5) v mid (1) v mid (2) v mid (3) v mid (4) v mid (5) i dd1 i dd2 0.8v dd 0.6v dd 0 0 50 v dd ?2.0 v dd ?1.5 0.5 1 / 2v dd ? 1.0 2 / 3v dd ? 1.0 2 / 3v dd ? 1.0 1 / 3v dd ? 1.0 1 / 3v dd ? 1.0 pin rst, cs, ck, di ki 1 ~ ki 5 rst, cs ,ck, di ki 1 ~ ki 5 rst, cs, ck, di rst, cs, ck, di ki 1 ~ ki 5 ki 1 ~ ki 5 do ko 1 ~ ko 6 ep 1 ~ ep 4 s 1 ~ s 42 com 1 ~ com 3 ko 1 ~ ko 6 ep 1 ~ ep 4 s 1 ~ s 42 com 1 ~ com 3 do com 1 ~ com 3 s 1 ~ s 42 com 1 ~ com 3 s 1 ~ s 42 com 1 ~ com 3 100 v dd ?1.0 v dd ?1.0 v dd ?1.0 1.0 1.0 1.0 0.2 (200 w ) 30 200 v dd v dd 0.2v dd 0.2v dd 6.0 6.0 0.05v dd 200 6.0 v dd ?0.5 2.0 1.0 0.5 (500 w ) 1 / 2v dd + 1.0 2 / 3v dd + 1.0 2 / 3v dd + 1.0 1 / 3v dd + 1.0 1 / 3v dd + 1.0 70 500 v v v v m a m a v k w m a v v v v v v v v v v v v v v m a m a v 1 = v dd v 1 = v ss v dd = 5.0v v o = v dd i o = ?1ma i o = ?300 m a i o = ?20 m a i o = ?100 m a i o = 50 m a i o = 300 m a i o = 20 m a i o = 100 m a i o = 1ma 1 / 2bias 1 / 3bias 1 / 3bias 1 / 3bias 1 / 3bias in sleep mode f osc = 38khz s not designed for radiation resistance.
5 standard ics BU9768AK / BU9768AKv ac timing characteristics (v dd = 4.5v to 6.0v, ta = 25?) parameter symbol min. typ. max. unit rise time fall time data setup time data hold time cs wait time cs setup time cs hold time ck high level time ck low level time d0 output delay time oscillation guaranteed range t u t d t s (1) t h (1) t cw t s (2) t h (2) t h t l t dl f osc 100 100 100 100 100 100 100 19 pin cs, ck, di cs, ck, di ck, di ck, di cs, ck cs, ck cs, ck ck ck do osc 38 300 300 200 (note 1) 76 ns ns ns ns ns ns ns ns ns ns khz (note 1) since do is open drain output, the output delay time varies depending on the pull-up resistance. (note 2) values measured for attachments of r = 47k w , c = 1000pf. (note 2) application example (1 / 2 bias mode) * the pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors. r 3 r 1 c 3 r 2 c 2 c 1 gnd m -com lcd panel com 1 com 2 com 3 ko 1 ko 2 ko 3 ko 4 ko 5 ko 6 ki 1 ki 2 ki 3 ki 4 ki 5 do di ck v dd 2 rst v dd osc s 1 (ep 1 ) ??????????? s 40 v dd 1 cs r 1 , c 1 : constants should be set to match data communications. r 2 : 47k w (fosc = 38khz) c 2 : 1000pf (fosc = 38khz) c 3 : ^ 0.047 m f r 3 :1k w ~ 10k w key matrix (30 maximum) fig. 2
6 standard ics BU9768AK / BU9768AKv (1 / 3 bias mode) r 3 r 1 c 3 c 3 r 2 c 2 c 1 gnd m -com lcd panel com 1 com 2 com 3 ko 1 ko 2 ko 3 ko 4 ko 5 ko 6 ki 1 ki 2 ki 3 ki 4 ki 5 do di ck v dd 2 rst v dd osc s 1 (ep 1 ) ?????????? s 40 v dd 1 cs r 1 , c 1 : constants should be set to match data communications. r 2 : 47k w (fosc = 38khz) c 2 : 1000pf (fosc = 38khz) c 3 : ^ 0.047 m f r 3 :1k w ~ 10k w key matrix (30 maximum) fig. 3 (1 / 2 bias mode) r 4 r 3 r 3 r 1 c 3 r 2 c 2 c 1 gnd m -com lcd panel com 1 com 2 com 3 ko 1 ko 2 ko 3 ko 4 ko 5 ko 6 ki 1 ki 2 ki 3 ki 4 ki 5 do di ck v dd 2 rst v dd osc s 1 (ep 1 ) ?????????? s 40 v dd 1 cs key matrix (30 maximum) r 1 , c 1 : constants should be set to match data communications. r 2 : 47k w (fosc = 38khz) c 2 : 1000pf (fosc = 38khz) r 3 : the constant should be set to match the panel, through testing or other means . c 3 : ^ 0.047 m f r 4 :1k w ~ 10k w fig. 4 * the pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors.
7 standard ics BU9768AK / BU9768AKv (1 / 3 bias mode) * the pull-up resistor value should be set to a value so that the waveform is not destroyed by the wiring capacitance or other factors. r 4 r 3 r 3 r 3 r 1 c 3 c 3 r 2 c 2 c 1 gnd m -com lcd panel com 1 com 2 com 3 ko 1 ko 2 ko 3 ko 4 ko 5 ko 6 ki 1 ki 2 ki 3 ki 4 ki 5 do di ck v dd 2 rst v dd osc s 1 (ep 1 ) ?????????? s 40 v dd 1 cs key matrix (30 maximum) r 1 , c 1 : constants should be set to match data communications. r 2 : 47k w (fosc = 38khz) c 2 : 1000pf (fosc = 38khz) r 3 : the constant should be set to match the panel, through testing or other means. c 3 : ^ 0.047 m f r 4 :1k w ~ 10k w fig. 5
8 standard ics BU9768AK / BU9768AKv circuit operation (1) data communications the BU9768AK / BU9768AKv are able to receive lcd display data output from the controller, as well as the results of key scans. 1) lcd display data output (from controller) when lcd data is output, the command code ?2?must be output at the beginning of the data. fig. 6 shows an example of lcd display data output. q during the time that cs is low, the command code ?2?is input synchronized to the ck clock, and cs is then set to high before the rise of the next ck clock. w the lcd data is sent, and 0 (low level) is input for the two bits following d 126 . e an 8-bit control code is input, and cs is set to low. cs ck di cs ck di lsb 000000 00 d 121 d 122 d 123 d 124 d 125 d 126 s 0 p 0 p 1 sc s 1 k 0 k 1 dp d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 11 msb command code: 42 1 byte (8 bits) lcd display data 1 byte (8 bits) lcd display data 1 byte (8 bits) a value of 0 low must always be input for the 2 bits following d 126 . control code 1 byte (8 bits) fig. 6 example of lcd display data transmission
9 standard ics BU9768AK / BU9768AKv segment data correspondence table com 3 d 1 (ep 1 ) d 4 (ep 2 ) d 7 (ep 3 ) d 10 (ep 4 ) d 13 d 16 d 19 d 22 d 25 d 28 d 31 d 34 d 37 d 40 d 43 d 46 d 49 d 52 d 55 d 58 d 61 com 2 d 2 d 5 d 8 d 11 d 14 d 17 d 20 d 23 d 26 d 29 d 32 d 35 d 38 d 41 d 44 d 47 d 50 d 53 d 56 d 59 d 62 com 1 d 3 d 6 d 9 d 12 d 15 d 18 d 21 d 24 d 27 d 30 d 33 d 36 d 39 d 42 d 45 d 48 d 51 d 54 d 57 d 60 d 63 s 22 s 23 s 24 s 25 s 26 s 27 s 28 s 29 s 30 s 31 s 32 s 33 s 34 s 35 s 36 s 37 s 38 s 39 s 40 ko 1 (s 41 ) ko 2 (s 42 ) s 1 (ep 1 ) s 2 (ep 2 ) s 3 (ep 3 ) s 4 (ep 4 ) s 5 s 6 s 7 s 8 s 9 s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 s 18 s 19 s 20 s 21 com 3 d 64 d 67 d 70 d 73 d 76 d 79 d 82 d 85 d 88 d 91 d 94 d 97 d 100 d 103 d 106 d 109 d 112 d 115 d 118 d 121 d 124 com 2 d 65 d 68 d 71 d 74 d 77 d 80 d 83 d 86 d 89 d 92 d 95 d 98 d 101 d 104 d 107 d 110 d 113 d 116 d 119 d 122 d 125 com 1 d 66 d 69 d 72 d 75 d 78 d 81 d 84 d 87 d 90 d 93 d 96 d 99 d 102 d 105 d 108 d 111 d 114 d 117 d 120 d 123 d 126
10 standard ics BU9768AK / BU9768AKv 1. if there is an unused segment output if there is segment output that is not used, depending on the panel, the transmission of the lcd display data can be simplified by deciding the pin or pins to be used starting from s 40 (s 42 if pins 44 and 45 are used as segment output, and s 41 if only pin 44 is used as segment output). this figure shows an example in which the 30 segment outputs from s 11 to s 40 are used, and assumes that commu- nication is done in units of eight bits (one byte). for this reason, the data of s 9 and s 10 (from d 25 to d 30 ), which are not used, is input as dummy data. if the unit is not eight bits, this dummy data can be omitted, in which case the data should be input after the command code, starting from the data of d 31 . however, even if pins 44 and 45 are used as key scan output and not as segment output, the data for d 121 to d 126 cannot be omitted. 2. control codes the BU9768AK is designed to support various applications, depending on the combination of control codes used. ?dp: display mode control depending on the type of display, either 1 / 2 bias drive or 1 / 3 bias drive may be selected. 1: 1 / 2 bias drive 0: 1 / 3 bias drive ?s 0 and s 1 : sleep mode control in the sleep modes, all displays are turned off, and the oscillation of the osc pin is stopped, enabling a lower power consumption. in sleep modes, although all of the displays are turned off, key scans are enabled. for information on key scans in the sleep modes, please refer to pages 15 to 22. various sleep modes can be selected, depending on the application. cs ck di cs ck di lsb 000000 00 d 121 d 122 d 123 d 124 d 125 d 126 s 0 p 0 p 1 sc s 1 k 0 k 1 dp d 25 d 26 d 27 d 28 d 29 d 30 d 31 d 32 11 msb command code: 42 1 byte (8 bits) lcd display data 1 byte (8 bits) lcd display data 1 byte (8 bits) a value of 0 low must always be input for the 2 bits following d 126 . control code 1 byte (8 bits) fig. 7 simplified data communication
11 standard ics BU9768AK / BU9768AKv control code key scan output mode segment / common output osc pin 0 0 1 1 s 0 s 1 0 1 0 1 ko 1 h l l h ko 2 h l l h ko 3 h l l h ko 4 h l l h ko 5 h l h h ko 6 h h h h normal sleep sleep sleep output fixed at low fixed at low fixed at low oscillating stopped stopped stopped in the sleep modes, oscillation of the osc pin stops, but if a button is pressed while the key scan output is on the high line, oscillation begins and a key scan is carried out. when the key scan has been completed, oscil- lation stops again. ?k 0 , k 1 : control that switches between key scan and segment output ?p 0 , p 1 : control that switches between segment and expansion pin output the output can be switched to match a variety of applications, depending on the combination of the four bits. control code key scan / segment segment / expansion pin max. no. of display segments max. key input 0 0 0 0 0 0 0 0 1 1 1 1 k 0 0 0 0 0 1 1 1 1 * * * * k 1 0 0 1 1 0 0 1 1 0 0 1 1 p 0 0 1 0 1 0 1 0 1 0 1 0 1 p 1 ko 1 ko 1 ko 1 ko 1 s 41 s 41 s 41 s 41 s 41 s 41 s 41 s 41 44pin ko 2 ko 2 ko 2 ko 2 ko 2 ko 2 ko 2 ko 2 s 42 s 42 s 42 s 42 45pin s 1 ep 1 ep 1 ep 1 s 1 ep 1 ep 1 ep 1 s 1 ep 1 ep 1 ep 1 1pin s 2 ep 2 ep 2 ep 2 s 2 ep 2 ep 2 ep 2 s 2 ep 2 ep 2 ep 2 2pin s 3 s 3 ep 3 ep 3 s 3 s 3 ep 3 ep 3 s 3 s 3 ep 3 ep 3 3pin s 4 s 4 s 4 ep 4 s 4 s 4 s 4 ep 4 s 4 s 4 s 4 ep 4 120 114 111 108 123 117 114 111 126 120 117 114 30 30 30 30 25 25 25 25 20 20 20 20 4pin * don't care ?sc: control switching the lcd display on and off switching the lcd display on and off can be done regardless of the input data. 1: display off 0: display on (when displayed, displays can be obtained in accordance with the input data.) note: when the power supply is turned on, the following settings are in effect for control codes. these initial settings for control codes should be changed to match the mode being used. when the power supply is turned on: (dp, s 0 , s 1 , k 0 , k 1 , p 0 , p 1 , sc) = (0, 0, 0, 1, 1, 0, 0, 0)
12 standard ics BU9768AK / BU9768AKv 2) transmission of key data a command code of ?3?should be input in order to output the results of a key scan to the BU9768AK / BU9768AKv. d 29 d 30 sa d 0 d 1 d 2 11 1 00 0 0 0 command code: 43 1 byte (8 bits) 32 bits if there is data in the key buffer, do will be low. fig. 8 transmission of key data cs ck lsb msb di do don't care if cs is changed to high level after the command code is input, the data in the key buffer is output synchronized to the rise of ck. key data correspondence table ko 1 (s 41 ) ko 2 (s 42 ) ko 3 ko 4 ko 5 ko 6 ki 1 d 1 d 6 d 11 d 16 d 21 d 26 ki 2 d 2 d 7 d 12 d 17 d 22 d 27 ki 3 d 3 d 8 d 13 d 18 d 23 d 28 ki 4 d 4 d 9 d 14 d 19 d 24 d 29 ki 5 d 5 d 10 d 15 d 20 d 25 d 30 ?the data d 0 , which is output synchronized to the rise of cs, is unstable and should not be used. the output sa of the 32nd bit is a state acknowledge signal and outputs the current BU9768AK / BU9768AKv mode. sa: state acknowledge signal in normal modes: sa = low in sleep modes : sa = high
13 standard ics BU9768AK / BU9768AKv (2) key scan operation with the BU9768AK / BU9768AKv, up to 30 key inputs can be received. ko 1 key on 15ms fig. 9 key scan operation ko 2 ko 3 ko 4 ko 5 ko 6 do when the key scan is completed without problems, do changes from high to low. one key scan requires 15ms (if f osc = 38khz, 582 / f osc (sec)). key scans which are shorter than this time cannot be received. also, in order to prevent chattering, the key scan waveform (ko output) reaches the high level twice dur- ing one key scan. after scanning has been carried out twice, the data from the two scans is compared, and if the data for all of the keys does not match, an error occurs. 1) key scans and key data communications with the BU9768AK / BU9768AKv, if normal key input is received, do changes from high to low, so if do is con- nected to the interrupt input pin of the controller, interrupt processing can be carried out based on the key input. also, after do changes to low following completion of a key scan, a new key scan cannot be carried out until all of the key data has been read. if multiple keys are pressed at once, multiple key data is set for the various key inputs to be distinguished. key1 key2 key3 do new key scan cannot be carried out until all data has been read. key scan key scan key scan key data reading data corresponding to one key scan fig. 10 relationship between key scan and data communications
14 standard ics BU9768AK / BU9768AKv 2) key scans in sleep modes in sleep modes, depending on the mode, the key scan standby state of the ko pin is restricted. the figure above assumes that the control codes s 0 and s 1 have been set to 0 and 1, respectively. in this case, if any key between key 26 and key 30 is pressed, an high level is input on the kin line, oscillation begins, and a key scan is carried out. if any key between key 1 and key 25 is pressed, all of the kin lines remain at low level, and no key scan is carried out. oscillation resumes when the key scan has been completed. if key input in a sleep mode is to be used and interrupt processing carried out, a key on a kon = high line should be used. key1 (l) ko 1 (l)ko 2 (l)ko 3 (l)ko 4 (l)ko 5 (h)ko 6 kl 1 kl 2 kl 3 kl 4 kl 5 key2 key3 key4 key5 key6 key7 key8 key9 key10 enlarged view of one key key11 key12 key13 key14 key15 key16 key17 key18 key19 key20 key21 key22 key23 key24 key25 key26 key27 key28 key29 key30 key input received standby state in sleep mode fig. 11 example of key matrix configuration (the diodes installed on each key are to prevent erroneous recognition if multiple keys are pressed.)
15 standard ics BU9768AK / BU9768AKv 3) operation flow in a key scan the flow of operations taking place during a key scan is shown below. the ?uccessful?judgment of the key scan shown in the illustration is based on the data from the two key scans matching for all of the keys, as described on page 13. if an error occurs, the key scan is carried out once again after the first key scan has been completed if a key has remained pressed, and continues to be carried out as long as the key is pressed, until it is successfully completed. after a key scan has been successfully completed, no new key scans can be carried out until reading of the key data has been completed. no no yes waiting for key input has key been input? was key scan successful? waiting for input of key data read code do ? low fig. 12 key scan flow key input (key scan starts) yes
16 standard ics BU9768AK / BU9768AKv (3) output waveforms 1) 1 / 2 bias mode (frame frequency = f osc / 384) v dd 1 / 2v dd com 1 v ss v dd 1 / 2v dd com 2 v ss v dd 1 / 2v dd com 3 v ss v dd 1 / 2v dd v ss v dd 1 / 2v dd sn v ss v dd 1 / 2v dd v ss v dd 1 / 2v dd v ss 1 frame when sn (d 3n-2 , d 3n-1 , d 3n ) = (0, 0, 0): out for all coms when sn (d 3n-2 , d 3n-1 , d 3n ) = (0, 0, 1): lights between com 1 and sn only when sn (d 3n-2 , d 3n-1 , d 3n ) = (1, 0, 1): out between com 2 and sn only when sn (d 3n-2 , d 3n-1 , d 3n ) = (1, 1, 1): lights for all coms
17 standard ics BU9768AK / BU9768AKv 2) 1 / 3 bias mode (frame frequency = f osc / 384) v dd 2 / 3v dd com 1 v ss v dd 2 / 3v dd com 2 v ss v dd 2 / 3v dd 1 / 3v dd 1 / 3v dd 1 / 3v dd com 3 v ss v dd 2 / 3v dd v ss v dd 2 / 3v dd sn v ss v dd 2 / 3v dd v ss v dd 2 / 3v dd 1 / 3v dd 1 / 3v dd 1 / 3v dd 1 / 3v dd v ss 1 frame when sn (d 3n-2 , d 3n-1 , d 3n ) = (0, 0, 0): out for all coms when sn (d 3n-2 , d 3n-1 , d 3n ) = (0, 0, 1): lights between com 1 and sn only when sn (d 3n-2 , d 3n-1 , d 3n ) = (1, 0, 1): out between com 2 and sn only when sn (d 3n-2 , d 3n-1 , d 3n ) = (1, 1, 1): lights for all coms
18 standard ics BU9768AK / BU9768AKv (4) rst and display control after the power supply has been turned on, because the internal data of the BU9768AK / BU9768AKv (d 1 to d 126 ) is unstable, rst goes low at the same time that the power supply is turned on. while rst is low, data is transmit- ted using the microcomputer, and when data transmission has been completed, rst can be set to high to prevent meaningless displays. (for the states of control codes when the power supply is turned on, see page 11.) in the circuit example shown above, the value of t1 is determined by the value of the capacitor and resistor. the value should be set in such a way that the constant determined by the capacitor and resistor is the initialized commu- nication time + t2. r v dd rst c gnd fig. 14 example of rst pin processing unstable fig. 13 communication, display and rst timing t 1 v il v dd cs internal data rst t 2 t1: communication time t2: 10 m s min. display and control data assured display display
19 standard ics BU9768AK / BU9768AKv operation notes (1) using the product with the synchronous clock stopped if the synchronous clock is to be stopped during the period that data is not being transmitted, program the product so that the rise of ck is input at least twice after the fall of cs. (2) precautions concerning key scans when the power supply is turned on to carry out a key scan immediately after the power supply is turned on, without transmitting data, the parameters must be set so that the following conditions are met. 1) the rise of the synchronous clock pulse is input to the ck pin at least twice. 2) since input can only be received from keys on the ko 3 to ko 6 line, other keys should not be used for functions such as interrupts. (for information on the status when the power supply is turned on, please see page 11.) * if data is being transferred before a key scan is carried out, after the power supply is turned on, these precautions do not apply. ck rises at least twice fig. 15 when ck is stopped at high cs ck ck rises at least twice cs ck fig. 16 when ck is stopped at low
20 standard ics BU9768AK / BU9768AKv external dimensions (units: mm) BU9768AK BU9768AKv qfp-a64 vqfp64 48 33 32 17 16 1 49 64 10.0 0.2 12.0 0.3 10.0 0.2 12.0 0.3 0.2 0.1 0.1 0.5 0.125 0.1 0.5 0.10 1.4 0.1 0.15 0.1 48 33 32 17 49 64 1 16 14.0 0.2 16.4 0.3 14.0 0.2 0.35 0.1 0.05 0.5 16.4 0.3 0.8 2.7 0.1 0.15 0 < t on < 10ms v dd ^ 4.5v v dd < 0.3v t wait ^ 1ms instruction receipt possible make sure of the following when resetting when the power is on. ? when using the external reset terminal, make rst = ??at 1ms or more with v dd at 4.5v or more. ? when not using the external reset terminal, v dd has to satisfy the following conditions.

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